Impulse CoValidator™ Test Bench Generator

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Registered in England No: 4264387
Registered Office: c/o Bulcock & Co. 10 The Bull Ring, Northwich, Cheshire, CW9 5BS, UK.

Kane Computing Ltd,
Suite I, Ascot Court,
71-73 Middlewich Road,
Northwich, Cheshire, CW9 7BP
United Kingdom
Tel: +441606351006
Fax: +441606351007
Email: Sales-Support-Marketing
©Copyright: KCL 1986-2012

Federation of Small Businesses

Impulse CoValidator™ Test Bench Generator

Features

Generate portable HDL test bench code ready for use with any IEEE standard simulator
Generate simulation test files from C-language software, for software and RTL equivalency checking
Generate ModelSim compatible simulator scripts, to run HDL simulation with a single command
Iteratively verify your design, from unit tests to a complete system test suite
Verify bit-accurate and cycle-accurate behavior or your Impulse C hardware module
Trace activity on inputs and outputs, using Impulse C-language APIs to describe streaming I/O
Generate and monitor an unlimited number of I/O streams, of any data width
Improve your design productivity by leveraging pre-optimized functions and open-source software
Reduce your project risk by reusing known-good C-language code for validation
Extend your CoValidator testing environment with customized, application specific producer and co
sumer functions – ask us for details

Ordering Info: Part No. Please Call

Description

Impulse CoValidator™ provides a fast path from C-language to hardware-accurate and bit-accurate RTL simulation. Use CoValidator with the Impulse CoDeveloper™ C-to-FPGA compiler to design FPGA hardware and hardware test bench elements using standard C. Verify the generated HDL with automatically generated HDL test benches, before synthesizing the HDL to a target FPGA device.

CoValidator lets you use standard C debuggers such as Visual Studio® to validate your application, then compare the results with hardware-accurate HDL simulation. Use C-Language for HDL test bench generatior to accelerate the FPGA development and debugging process. Use third-party and open source librariess to generate streams of input data, for example using standard-format audio, image or video files. CoValidator generates HDL compatible with all IEEE-compliant VHDL simulators, and also generates scripts for ModelSim® letting you generate HDL test benches and launch simulation with just a few keystrokes. Catch errors before going through FPGA synthesis and and place-and-route, and save hours, days or even weeks off of your development time.

Related Products

Impulse C™ C-Language Development Tool (development tool for FPGA accelerated computing)
Impulse CoDeveloper™ Video Development Kit (high throughput streaming video)
Impuse CoDeveloper™ Embedded/DSP Kit (DSP application development)
Impulse C™ FPGA Image Processing Library (accelerate image processing development)
Impulse C™ FPGA math.h Library for FPGAs (accelerate FPGA based algorithm development)

Downloads

Datasheet (PDF 523KB)

Links

Impulse Accelerated Technology's web site