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Registered in England No: 4264387
Registered Office:
c/o Bulcock & Co. 10 The Bull Ring, Northwich, Cheshire, CW9 5BS, UK.

Kane Computing Ltd,
Suite I, Ascot Court,
71-73 Middlewich Road,
Northwich,
Cheshire, CW9 7BP
United Kingdom
Tel: +441606351006
Fax: +441606351007
Email: Sales-Support-Marketing
©Copyright: KCL 1986-2012

Federation of Small Businesses

PARS - Parallel Application from Rapid Simulation

Features

  • Target embedded systems consisting of TI DSP (C64xx, C67xx) and Xilinx FPGA
  • Manages all inter-processor communication and synchronization
  • Generates test benches for Hardware-In-The-Loop simulation
  • Generates stand-alone (ROM-able) applications
Ordering Info: Part No. PARS

Description

Parallel Application from Rapid Simulation (PARS) is a toolbox for 'The MathWorks' MATLAB® and Simulink®. This enabling technology allows a user to design an entire system within the MATLAB and Simulink environment and then automatically generate code for multi-DSP and multi-FPGA in the system, without writing a single line of C or VHDL code. All the inter-processor communication and synchronization code is built into the single application file. The generated application code will also contain all of the booting information for the entire multi DSP/FPGA platform. This advanced, but easy to use, tool also provides Hardware-In-the-Loop (HIL) capability to test the application on the hardware in real time.

PARS is a new and emerging technology for generating parallel applications that target hardware systems comprising multiple DSP and FPGAs from a single Simulink model. There are many software packages in the market that target a single DSP or FPGA from a Simulink model but so far none of them supports multiple DSPs and FPGAs and could generate a single application image.

PARS accepts a Simulink model as input, and helps users to partition the Simulink model into several tasks which will be placed on different DSPs, General purpose processors and/or FPGAs. PARS helps users calculate the size and type of all data transfers between different tasks and then generates the C source code with all necessary inter-task/inter-processor communication functions.

PARS compiles, links and then configures the various generated tasks to build a single application file, suitable for downloading into the parallel processing network. All the booting and task placement information is built into the application file together with all bit streams for the FPGAs in the system.

PARS checks the Simulink model for the presence of any possible deadlock and in case it finds any deadlock in the model, PARS tries to resolve them. In cases where the deadlock could not be resolved automatically, it will report the source of deadlock and guides the user to resolve it manually.

Related Products

  • 3L Diamond (multiprocessor tool suite - Sundance Edition)
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Downloads

PDF User Guide (PDF ??KB)

Links

Web Page Sundance's web site

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