Altera FPGA eNews - July 2008

Dear Customer,

Please find details of new products from Altera, Bitec and Microtronix, which offer new Altera Cyclone® FPGA and Video Development Kits, Processor Modules and IP Core Development Solutions.

PRODUCTS

• Altera Cylcone® III Development Base Kit
• Bitec Cyclone® III Video Development Kit
• ViClaro III HD Video Development Kit
• ViClaro II HD Video Enhancement Development Platform
• Lancelot VGA ID Design Kit
• FireFly II Module Altera Cyclone® II RoHS Compliant Modules
• FireFly II PSK Development Kit to add Santa Cruz Cards
• I2C IP Core
• Avalon Multi-port SDRAM Memory Controller IP Core
• LVDS Transmitter/Receiver IP Core
• Streaming Multi-port SDRAM Memory Controller IP Core
• Hyperdrive Multi-port DDR2 Memory Controller IP Core

VIDEO IMAGING DEVELOPMENT BOARD SOLUTIONS

The DSP Development Kit, Cyclone® III Edition is RoHS compliant and delivers a complete digital signal processing (DSP) development environment for design engineers. The kit facilitates the entire design process from design conception through hardware implementation. The kit includes the Cyclone® III development board, the data conversion high-speed mezzanine card (HSMC), the DSP builder development tool, Quartus® II development software, MATLAB/Simulink evaluation software, evaluation intellectual property (IP) cores, design examples, power supplies, cable and documentation.

The Bitec Video Development Kit provides a cost effective, integrated solution for developers wishing to utilise the Cyclone III device for video application development. Based on teh Altera Cyclone Development Kit, the Video Development Kit enables designs to interface to a wide variety of video devices via two High-Speed Mezzanine Connector (HSMC) daughter cards.

The Microtronix ViClaro III HD Video IP Dev Kit is a versatile video and imaging processing IP development platform supporting all the interfaces for HD video display and imaging applications typically required by consumer, automotive and medical market segments. Designed in conjunction with Altera®, the kit includes a suite of video processing IP reference examples, to provide a solid starting point for building your next generation HD 1080p 100/120 Hz video display product. The kit offers an unprecedented level of system integration to address the market needs for a flexible and powerful DVI, HDMI, SDI, HD/HDTV and PCIe engineering design-evaluation platform for the development of video processing IP algorithms.

The innovative Lancelot VGA Video Controller IP Core Solution is for customers wanting to develop video IP based solutions. The Lancelot Kit comes complete with an IP core written in VHDL that can be synthesized for all Altera FPGA devices. The Kit comes with a small hardware board that includes a 24-bit RAMDAC, VGA connector, stereo audio connector, and 2 PS/2 connectors. The daughter board connects using Santa Cruz expansion headers. The Kit will display an image up to 1024x768 pixels and 24-bit colour.

CONFIGURABLE PROCESSOR MODULE SOLUTIONS

The Firefly® II Configurable Processor Module combines the benefits of an off-the-shelf module with the flexibility of an FPGA with hardware DSP support. This “computer on a board” comes complete with a processor and memory. Just plug the Firefly II module into your project and you can quickly go from design to prototype to product stages.

The Product Starter Kit comes with a Cyclone II Firefly module and a base board that includes two Santa Cruz expansion headers. Providing you with the flexibility to build and the freedom to design. Also, no special programming cable is required since the USB Blaster cable technology is built right into the board! Developers can then select up to two modules.

IP CORE DEVELOPMENT SOLUTIONS

The I2C Master/Slave/PIO IP Core is a complete I2C solution offering three modes of operation: I2C Master controller, I2C Slave controller and an I2C Slave PIO device. Three I2C bus transmission speeds are supported; Normal: 100Kbps, Fast: 400Kbps and High: 1Mbps. The Microtronix I2C Master/Slave core provide a generic memory-mapped bus interface. It is also designed as an Altera SOPC Builder ready component and integrates easily into any SOPC Builder generated system using an Nios® II Avalon bus. The Microtronix I2C Slave PIO core supports up to four 8-bit I/O ports for a total of 32 I/O pins. It is provided as an Altera Quartus II Megafunction and integrated into the Altera MegaWizard Plug-in Manager.

The Microtronix High Performance Avalon Multi-port SDRAM Memory Controller IP Core is designed for building low latency Avalon multi-master streaming data systems. Advanced design features enable maximum system clock rates using low speed FPGA's and standard memory devices. *The increased memory performance gives you flexibility and freedom to design with fewer memory components, lowering your production cost, and saving you money. (*Configuration dependent).

The Microtronix Video LVDS SerDes Transmitter / Receiver IP Core provides a complete, easy-to-use Serializer/Deserializer (SerDes) solution to interface a wide variety of video host systems to Flat Panel displays. The Transmitter and Receiver cores support both 28 bit (8 bit RGB) and 35 bit (10-bit RGB) parallel data configurations using either 4 or 5 LVDS serial channels. Transmitter and Receiver cores can be cascaded to create dual and quad LVDS links supporting display panel resolutions up to 1080p at 120 Hz and beyond.

The Microtronix Streaming Multi-port SDRAM Memory Controller IP Core integrates: a burst SDRAM memory controller core, a port arbitrator and intelligent look-ahead FIFO controller into one easy-to-use core. By supporting SDR & DDR / DDR2 and Mobile DDR device families in a single IP Core assures designers of a smooth low-risk migration path with changing technology.

The Microtronix HyperDrive Multi-port DDR2 Memory Controller IP Core levitates FPGA based hardware designs to a whole new level of performance. Built around a new DDR2 state machine controller, and an interleaved FIFO architecture which allows the local bus data path to operate at either full-rate, (twice the DDR2 data bus width) or at half-rate with a bus width of four times the DDR2 data bus interface. In a Cyclone device, the local bus operates at half-rate only. A proprietary Microtronix data capture technique enables 400 MHz DDR2 performance in a Stratix II device.