The PROC_SoC3 and PROC_SoC10 are GiDEL's third-generation ASIC Prototyping Systems. Featuring the industry's largest and fastest FPGA, the Stratix IV E FPGA-based PROC-SoC ASIC Prototyping Systems are designed to debug and verify today's most advanced SoC designs. The PROC_SoC3-4S is able to support designs up to 36 million ASIC gates and the PROC_SoC10-4S is able to support designs up to 120 million ASIC gates. By leveraging the system's flexible architecture, both ASIC prototyping systems can be connected to provide support for up to 360 million ASIC gates. The systems are architected and designed to operate at system clock speeds up to 300MHz.

TotalHistory is a software only solution enabling users to define a list of signals in the design which they want to trace at full system speed. There is practically no limit on the number of signals traced. The user can then view the trace using a waveform viewer to debug and validate the design. Optionally, an API is available for queries by advanced users.

The Impulse financial feed handling platform enables UDP input directly to FPGA hardware, as well as PCI Express processing for FPGA-to-host communications. The FPGA hardware platform and the Impulse C programming tools can be used to identify specific stocks and price levels, and transfer messages to a host processor.