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FPGA eNews from KCL - April 2009
I am pleased to provide news of new products that I hope you will find interesting, special offers and a questionnaire (with free gift).
PRODUCTS
- Free 1080PiP Reference Design with Cyclone III Video Development Kit (VDK)
- Altera Video Processing Reference Design for Up Conversions
- Timing Driven Simulink FPGA Solutions
- New SDI Input/Output Card for Cylone III
- Discount Vouchers with Microtronix Altera Development Boards
- HD Video Development Project Questionnaire
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Free 1080PiP Reference Design with Cyclone III Video Development Kit (VDK) |
Buy a complete Cyclone III VDK from KCL and get a free 1080PiP Reference Design.
The kit’s 1080p PiP reference design combines a single composite/s-video channel with a full HD 1080p video stream to generate a 1080p PiP output video stream. The resulting image stream is the combination of both input video signals.
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Altera Video Processing Reference Design for Up Conversions |
Altera’s updated Video Processing Reference Design demonstrates up conversion from an SD video stream in NTSC format and picture-in-picture (PiP) mixing with a background layer. The video stream is output in HD (1024×768) over a digital video interface.
This reference design uses the latest version of IP cores from Altera’s Video & Image Processing (VIP) Suite, including the scaler (polyphase mode), deinterlacer (motion adaptive mode), and alpha blending mixer cores.
Download the reference design today to get started on your next video processing project!
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Timing Driven Simulink FPGA Solutions |
Simulink is popular among DSP designers, and FPGA vendors have taken note. These vendors have created blockset libraries that enable Simulink designs to be synthesized for FPGA implementation. While these blocksets are useful, DSP designers have lacked an automated method to transform the Simulink design to a timing-optimized FPGA implementation.
The latest system design tools, including Altera’s DSP Builder, offer timing-driven Simulink synthesis that enables automatic generation of timing-optimized HDL. This means that the HDL generated by DSP Builder now meets the timing constraints set within Simulink.
See the design productivity advantages of using these tools, along with examples, in this article.
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New SDI Input/Output Card for Cylone III |
SDALTEVK is a triple-rate SDI and video clocking daughter card for the Altera Cyclone III Development Kit. The kit provides broadcast video system designers a comprehensive platform for rapid evaluation and prototyping of new designs to reduce time to market. National's daughter card, SDALTEVK, includes synthesizable FPGA source available in both Verilog and VHDL to maximise flexibility and facilitate IP customisation. The daughter card plugs directly into the Altera Cyclone III Development Board via Altera's high-speed mezzanine connector (HSMC).
Email sales@kanecomputing.com for further information. |
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Discount Vouchers with Microtronix Altera Development Boards |
For a limited period KCL are offering discount vouchers for a second Microtronix ViClaro III HD Video Development Kit when the initial board is purchased.
Alternatively a low cost version is available that does not include Microtronix IP Cores, i.e.
- Avalon Multi-port DDR2 Memory Controller IP Core
- Video LVDS Transmitter / Receiver IP Core
- I2C Master Controller IP Core
Alternatively a lower cost version is available with 1 year Open Core Plus licences.
Email us at sales@kanecomputing.com for a quotation. |
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HD Video Development Project Questionnaire |
Are you planning an HD Video FPGA based development project? If so, click here to answer our brief questionnaire. All completed questionnaire will be entered in a prize draw for a £10 Amazon voucher.
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This eNews is published by Kane Computing Ltd, distributors of DSP/FPGA, Broadcast, Image Processing, Machine Vision, Audio/Video Compression and Telecommunications Solutions.
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Copyright: Kane Computing Ltd 2009
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