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Registered in England No: 4264387
Registered Office: c/o Bulcock & Co. 10 The Bull Ring, Northwich, Cheshire, CW9 5BS, UK.

Kane Computing Ltd,
Suite I, Ascot Court,
71-73 Middlewich Road,
Northwich, Cheshire, CW9 7BP
United Kingdom
Tel: +441606351006
Fax: +441606351007
Email: Sales-Support-Marketing
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Federation of Small Businesses

GDD9000 - DSP Vector and Matrix Library - ECC-BLAS-1/2/3

GDD Libraries

Features

  • Compatible with C62x, C64x, C6701 and C6711
  • 90 functions and macros
  • Basic linear algebra subroutines
  • Native floating point arithmetic
  • Floating point aritmetic
  • Real and complex data vectors and matrices
  • Big Endian (BE) or Little Endian (LE) (as xx suffix to part number)

 
Ordering Info: Part No. GDD9000-xx

Description

GDD9000 is a Floating Point Extended C Callable BLAS (Basic Linear Algebra Subroutines) Library for TMS320C6000.

The library is a set of about 90 functions and macros that implement the Basic Linear Algebra Subroutines standard for Level 1 BLAS vector-vector (O(n) complexity) operations, Level 2 BLAS matrix-vector (O(n^2) complexity) operations and Level 3 BLAS matrix-matrix (O(n^3) complexity) operations. These operations are performed on IEEE-754 single and double precision floating point format numbers. The library uses native floating point arithmetic support on the TMS320C67xx DSP and software simulates floating-point arithmetic for the fixed point DSP members of the C6000 family. The library processes both real and complex data vectors and matrices.

A set of memory allocation functions provides economical storage for general/structured matrix classes; minimizing the amount of RAM required to store structured matrices, such as symmetric, band and triangular classes of matrices.

The library is supported for use in any development environment using TI Code Generation Tools for the TMS320C6000 DSP and supports both big endian and little endian memory formats. All the functions are C callable and comply with TI's C environment calling conventions.

The library's functions have been optimised algorithmically at assembly level to fully utilize advantages of TMS320C6000 parallel architecture, floating-point arithmetic and pipeline. Level 1 functions are hand-coded in assembly to obtain maximum possible performance from the TMS320C6000 DSPs.

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Downloads

Datasheet (PDF 70KB)

 

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